2012, English, Thesis edition: Computer bus interconnect coding and optimisation Chen, Ge, Electrical Engineering & Telecommunications, Faculty of Engineering, UNSW

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Physical Description
  • Thesis
  • PhD Doctorate
Published
  • University of New South Wales. Electrical Engineering &​ Telecommunications, 2012
Language
  • English

Edition details

Title
  • Computer bus interconnect coding and optimisation
Author
  • Chen, Ge, Electrical Engineering &​ Telecommunications, Faculty of Engineering, UNSW
Other Contributors
  • Saeid , Nooshabadi, Electrical Engineering &​ Telecommunications, Faculty of Engineering, UNSW
  • Steven, Duvall, Electrical Engineering &​ Telecommunications, Faculty of Engineering, UNSW
Published
  • University of New South Wales. Electrical Engineering &​ Telecommunications, 2012
Physical Description
  • Thesis
  • PhD Doctorate
Subjects
Summary
  • Interconnects become a major bottleneck for deep sub-micron technologies. Interconnect design plays an important role in optimizing the performance of the interconnect in the modern VLSI system. The goal of optimizing the bus interconnect is to achieve high speed, energy effciency and reliability of on-chip communications. This dissertation develops a set of methods and coding schemes to ameliorate these problems. These methods were developed after a review of the models for evaluating the performance of on-chip interconnections, and they aim to optimize the bus system from the physical design level up to the system architecture level. The crosstalk effects on the bus energy delay and noise are quantifed as a function of the transition patterns in the sub-micron interconnection model. Next, a memoryless coding scheme is proposed to reduce the energy consumption of the bus interconnection; the coding circuits are simple and simulation studies show that the energy reduction is superior 21% energy saving compared to uncoded bus. A memory coding scheme has limited energy effciency due to the exponential increase in coding circuitry. A hybrid transition pattern coding scheme is presented to reduce both energy consumption and bus delay. The results demonstrate that the reduction is significant, up to 56% energy saving, and 67% energy delay saving compared to the uncoded scheme. Two signalling schemes are proposed and implemented. A low-swing driver circuit is integrated with charge recycling mechanics to boost the energy reducing performance on the on-chip interconnect. The proposed driver does not need an extra supply rail to turn the driver circuit into low-swing mode. A comprehensive analysis of energy consumption, delay and noise on 65 nm technology is presented. The proposed scheme can obtain 52% energy saving compared to the conventional CRT driver scheme. Another adaptive driver scheme is proposed to dynamically adjust the voltage levels on the bus depending on the error profiles. This scheme is beneficial to use in the random noisy environment while achieving low energy consumption if noise is absent. Next, a serial error correction code is proposed to not only prevent error occurrence, but also to correct error. Simulation studies show that it achieves significant energy reduction compared to an uncoded bus by using serialization techniques. In conclusion, this dissertation shows that through the use of a variety of methods, low energy, low latency and reliability is achievable in the deep sub-micron Complementary Metal-Oxide-Semiconductor (CMOS) process. Selection of appropriate scheme is dependent on the application scenario where the trade-off between energy dissipation, speed and implementation complexity is considered.
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Language
  • English

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